logic simulation

Design of a Platform for Logic Simulation and Testing

一种逻辑仿真测试平台的设计

Precise Sound Velocity Instrument and Its Logic Simulation

精密声速仪及其逻辑仿真

Research and Implementation of Parallel Logic Simulation System Based on VHDL

基于硬件描述语言的并行逻辑模拟系统研究与实现

The Application of Structured Design Strategies in Logic Simulation

结构化风格在逻辑模拟中的应用

Logic simulation is a necessary step in design of ASIC .

逻辑模拟是ASIC设计中必不可少的一个环节。

Complex business logic simulation with runtime variable state machine .

包含运行时变量状态机的复杂业务逻辑模拟。

Fuzzy logic simulation modeling and its application in the analysis of Qingdao fog

模糊逻辑仿真建模及其在青岛海雾分析中的应用

Event - Drive Digital Logic Simulation Tool

基于事件驱动的数字逻辑功能仿真工具

The Applications of Binary Decision Diagrams in Logic Simulation

二元判定图在逻辑模拟中的应用

A Set of Data Description Table and Time Queue Table Structure which Simplified the Logic Simulation Algorithm

一组简化逻辑模拟算法的数据描述表和时间队列表结构

Digit Circuit Logic Simulation Based on PROLOG Language

基于PROLOG语言的数字电路逻辑模拟

Research on logic simulation intelligent tutoring authoring environment

逻辑模拟智能教学写作环境的研究

Interface Logic Simulation Analyzing on High Speed Solid-state Storage Technique with CompactFlash Card Array

高速CF卡阵列固态存储技术的接口逻辑仿真分析

Dynamic load balancing in time warp-based parallel logic simulation

基于时间偏差的并行逻辑模拟的动态负载平衡

TJGS : A Process-Oriented Logic Simulation System Based on Compiler and Sort

TJGS：基于编译和排序的面向过程的逻辑模拟系统

The design , now , has passed the logic simulation successfully in Daisy computer workstation .

目前，线路级的设计已经完成，并且成功地通过了Daisy工作站的计算机逻辑模拟。

To reduce the simulation time of large circuits , parallel logic simulation has attracted considerable interest in recent years .

为减少大规模电路的模拟时间，近年来大家的兴趣转向了并行模拟。

An Algorithm for Multi & level Logic Simulation Mixed at the Register-Transfer , Functional and Gate Level

一种寄存器级与门级和功能级混合的模拟方法

High cost-time of logic simulation becomes a bottleneck of IC design , and cost of development is increased .

逻辑模拟的高耗时性成为IC设计的一个瓶颈，增加了开发成本。

SIM : An Advanced Interactive Mixed-Level Logic Simulation Tool

一个功能较强的交互式混合级逻辑模拟工具SIM

With the rapid growth of complexity of VLSI , more and more logic simulation has adopted parallel discrete event simulation .

随着大规模集成电路的复杂性日益增加，逻辑模拟开始采用并行离散事件模拟技术。

Boole process-based parallel algorithm for logic simulation

基于Boole过程的并行逻辑模拟算法

The whole processing of timing verification contains a gate-level static timing analysis and a logic simulation with accurate delay information .

整个处理器的时序验证包括门级静态时序分析和带精确延迟的逻辑模拟。

Complete the design and integration of other modules , the USB PHY module rigorous digital logic simulation , and analysis the simulation results .

在完成设计并整合其他的模块后，对整个USBPHY模块进行了严谨的数字逻辑仿真，并且针对仿真结果进行了分析。

Logic simulation is an important component of EDA software , and is an important tool that is employed to verify the correctness of design .

逻辑模拟是EDA软件的重要组成部分，是用来检验电路设计正确性的重要工具。

Waveforms are used as a tool for describing circuits during logic simulation and accurate simulation is achieved by computing and checking waveforms .

在逻辑模拟中用波形作为电路状态的描述工具，通过对波形的计算和检查实现精确的模拟。

Through the analysis and comparison of the three programs of the realization of logic simulation , determined the need for multi-FPGA system implementation and feasibility .

本文首先通过对实现系统逻辑仿真的三种方案进行分析比较，确定多FPGA系统实施的必要性和可行性。

Then , a linear-time partitioning algorithm based on a linear ordering of nodes in a circuit for parallel logic simulation is presented .

然后，提出一种在对电路中节点进行线性排序的基础上的线性时间划分算法。

The current algorithms for logic simulation are event-oriented . A process-oriented , highly time-parallel algorithm , called waveform algorithm is first presented in this paper .

本文阐述的波形法模拟算法是一个面向过程的，在时间上高度并行的逻辑模拟算法。

In this paper , an efficient method integrating logic simulation and Boolean satisfiability ( SAT ) is presented , which can verify the designs with black boxes .

该文提出了一种结合逻辑模拟和布尔可满足性的黑盒验证方法，用于验证设计中黑盒外部的功能正确性。